1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a charge pump circuit adopted in a delay locked loop (DLL) or a duty cycle correction circuit.
2. Description of the Related Art
Charge pump circuits are used as integrators when a node of a circuit needs to be charged to a predetermined voltage level. When a charge pump circuit is used in a DLL, the charge pump circuit serves to receive a pump-up control signal or a pump-down control signal and integrate them. When a charge pump circuit is used in a duty cycle correction circuit, the charge pump circuit receives a clock signal to integrate a logic xe2x80x9chighxe2x80x9d interval of the clock signal with a negative (or positive) slope and integrate a logic xe2x80x9clowxe2x80x9d interval of the clock signal with a positive (or negative) slope. If a duty cycle of the clock signal is on the order of 50%, a constant voltage is output, if a duty cycle is below 50%, an increasing (or decreasing) voltage is output, and if a duty cycle is over 50%, a decreasing (or increasing) voltage is output.
Various types of charge pump circuits have been developed, and representative charge pump circuits are introduced by John W. Poulton in, xe2x80x9cDigital System Engineeringxe2x80x9d, pp. 626-627, Cambridge University Press, 1998. Furthermore, U.S. Pat. No. 5,473,283 titled xe2x80x9cCascode Switched Charge Pump Circuitxe2x80x9d issued to Thomas M. Luich on Dec. 5, 1995 discloses improved charge pump circuits.
FIG. 1 is a circuit diagram showing an example of a conventional charge pump circuit of the type disclosed in xe2x80x9cDigital System Engineeringxe2x80x9d and. U.S. Pat. No. 5,473,283. The conventional charge pump circuit shown in FIG. 1 includes a pull-up current source 102, a first switching device 104 connected between the pull-up current source 102 and an output node 110. The switching device 104 is switched in response to a pump-up control signal PU. A second switching device 108 is connected between the output node 110 and a pull-down current source 106 and is switched in response to a pump-down control signal PD. A reference current source 116 provides a reference current Iref, and an integration capacitor Cint is connected to the output node 110 for integrating a current flowing through the output node 110 to change the current into a voltage.
The pull-up current source 102 includes a current mirror composed of PMOS transistors 112 and 114, and the pull-down current source 106 includes a current mirror composed of NMOS transistors 118 and 120. The first switching device 104 and the second switching device 108 are formed of a PMOS transistor and an NMOS transistor, respectively. However, the conventional charge pump circuit shown in FIG. 1 has a problem in that a coupling effect occurs due to overlap gate-to-drain capacitance Cca of the first switching device 104 and overlap gate-to-drain capacitance Ccb of the second switching device 108. The coupling effect refers to coupling of a signal of the output node 110, i.e., waveform of an output signal VO, due to overlap capacitances Cca and Ccb as the level values of a pump-up control signal PU and a pump-down control signal PD are changed.
Furthermore, the conventional charge pump circuit shown in FIG. 1 has a problem in that charge injection occurs due to parasitic capacitance Cpa existing at a junction N1 between the pull-up current source 102 and the first switching device 104, and parasitic capacitance Cpb existing at a junction N2 between the pull-down current source 106 and the second switching device 108. Specifically, as the first switching device 104 is turned on or off, the level of the junction N1 discontinuously swings from a power voltage VDD to an output voltage VO or vice versa. Furthermore, as the second switching device 108 is turned on or off, the level of the junction N2 discontinuously swings from a ground voltage VSS to the output voltage VO or vice versa. In this case, charges are injected from the parasitic capacitances Cpa and Cpb, and the injected charges are shared with the integration capacitor Cint. This effect is referr d to as charge injection.
The presence of coupling and charge injection may result in integration errors. In the conventional charge pump circuit shown in FIG. 1, if one or more cycles of pump-up and pump-down control signals PU and PD lapse, coupling does not exist but charge injection still remains.
FIG. 2 is a circuit diagram showing another example of a conventional charge pump circuit of the type disclosed in xe2x80x9cDigital System Engineeringxe2x80x9d, which is intended to prevent the charge injection effect. In addition to components of the charge pump circuit of FIG. 1, the conventional charge pump circuit shown in FIG. 2 further includes a switching device 104a connected between the pull-up current source 102 and compensating output node 111 and switched in response to an inverted signal {overscore (PU)} of the pump-up control signal, a switching device 108a connected between the compensating output node 111 and the pull-down current source 106 and switched in response to an inverted signal {overscore (PD)} of the pump-down control signal, and a unity gain buffer 122 the input terminal of which is connected to the output node 110 and the output terminal of which is connected to the compensating output node 111.
In the conventional charge pump circuit shown in FIG. 2, the voltage of the compensating output node 111and that of the output node 110 are made equal by the unity gain buffer 122. Furthermore, since either the switching device 104 or the switching device 104a and either the switching device 108 or the switching device 108a are always turned on, the levels of the junction N1 and the junction N2 do not swing discontinuously. Accordingly, this can prevent the possibility of charge injection.
However, the charge pump circuit shown in FIG. 2 requires the ideal gain and offset of the unity gain buffer 122 and very quick response time. In other words, the output resistance of the unity gain buffer 122 must be quite small and the operation speed thereof must be very fast. Thus, to achieve these characteristics, the charge pump circuit has disadvantages in that the layout area of the unity gain buffer 122 is increased and a large amount of power is consumed.
To solve the above problems, it is an objective of the present invention to provide a charge pump circuit capable of preventing the coupling effect and charge injection without an increase in a layout area and power consumption.
Accordingly, to achieve the above objective, the present invention provides a charge pump circuit including an output node, a first current source for sourcing pump-up current to the output node, and a first switching device which is connected between a first reference voltage node and the first current source and is switched in response to a pump-up control signal. A second current source sinks pump-down current from the output node, and a second switching device is connected between the second current source and a second reference voltage node and is switched in response to a pump-down control signal.
The charge pump circuit further includes a first dummy capacitor one end of which is connected to a junction between the first switching device and the first current source, and a second dummy capacitor one end of which is connected to a junction between the second switching device and the second current source. The opposite ends of the first and second dummy capacitors are connected to an inverted version of the pump-up control signal and an inverted version of the pump-down control signal, respectively.
Preferably, the first current source includes a current mirror for providing the pump-up current depending on a predetermined reference current. The second current source includes a current mirror for providing the pump-down current depending on the predetermined reference current.
The present invention also provides a charge pump circuit including first through fourth current sources, first through fourth switching devices, and first through fourth dummy capacitors. The first current source sources first pump-up current to the first output node, and the second current source sinks first pump-down current from the first output node. The first switching device is connected between a supply voltage node and the first current source and is switched in response to a pump-up control signal, while the second switching device is connected between the second current source and a ground voltage node and is switched in response to a pump-down control signal. The third current source sources a second pump-up current to the second output node, and the fourth current source sinks a second pump-down current from the second output node. The third switching device is connected between the supply voltage node and the third current source and is switched in response to an inverted signal of the pump-up control signal, and the fourth switching device is connected between the fourth current source and the ground voltage node and is switched in response to an inverted signal of the pump-down control signal.
One end of the first dummy capacitor is connected to a junction between the first switching device and the first current source, while the other end is connected to an inverted version of the pump-up control signal. One end of the second dummy capacitor is connected to a junction between the second switching device and the second current source, while the other end is connected to an inverted version of the pump-down control signal. One end of the third dummy capacitor is connected to a junction between the third switching device and the third current source, while the other end is connected to an inverted version of the pump-up control signal. One end of the fourth dummy capacitor is connected to a junction between the fourth switching device and the fourth current source, while the other end is connected to an inverted version of the pump-down control signal.
Preferably, the first current source includes a current mirror for providing the first pump-up current depending on a predetermined reference current. The second current source includes a current mirror for providing the first pump-down current depending on the predetermined reference current. The third current source includes a current mirror for providing the second pump-up current depending on the predetermined reference current. The fourth current source includes a current mirror for providing the second pump-down current depending on the predetermined reference current.